MIL-STD-1285D
APPENDIX L
L.3.4 Functional marking.
L.3.4.1 Terminal index feature. An index feature shall be visible from the top or bottom of microelectronic circuit packages and located near the package periphery.
L.3.4.1.1 Peripheral lead packages. For the peripheral lead packages (flat pack and dual-in-line), convention shall be that when viewed from the top, terminal number 1 shall be adjacent to or immediately counterclockwise from the index feature. Other terminal positions shall then be successively numbered counterclockwise from terminal 1.
L..3.4.1.2 Axial lead packages. For axial lead packages, convention shall be that when viewed from the bottom, terminal 1 shall be the next terminal position clockwise from the terminal index feature.
L.3.5 Identification marking location.
L.3.5.1 Marking location and sequence. The QML (when applicable) part number, date code and ESDS identifier, if applicable shall be located on the top surface of leadless or leaded chip carrier packages, pin grid array packages, flat packages, or dual-in-line configurations and on either the top or the side of cylindrical packages (TO configurations and similar configurations). When the size of a package is insufficient to allow marking of special process identifiers on the top surface, the backside of the package may be used for these markings except the ESDS identifier, if applicable shall be marked on the top. Button cap flat packs with less than or equal to 16 leads may have the identifier marked on the ceramic. Backside marking with conductive or resistive ink shall be prohibited. For unpackaged the marking shall be located on the container. For unpackaged die, marking is to be located on the container.
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